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th50vsf3582/3583aasb 2001-06-08 1/50 ? function mode control for flash memory compatible with jedec-standard commands ? flash memory functions simultaneous read/write operations auto-program auto chip erase, auto block erase auto multiple-block erase program suspend/resume block-erase suspend/resume data polling/toggle bit function block protection/boot block protection automatic sleep, hidden rom area supports common flash memory interface (cfi) byte/word mode ? erase and program cycle for flash memory 10 5 cycles (typical) ? boot block architecture for flash memory th50vsf3582aasb: top boot block TH50VSF3583AASB: bottom boot block ? package p-fbga69-1209-0.80a3: 0.31 g (typ.) tentative toshiba multi-chip integrated circuit silicon gate cmos sram and flash memory mixed multi-chip package description the th50vsf3582/3583aasb is a mixed multi-chip package containing a 8,388,608-bit full cmos sram and a 33,554,432-bit flash memory. the cios and ciof inputs can be used to select the optimal memory configuration. the power supply. flash memory a simultaneous read/write operation so that data can be read during a write or erase operation. the th50vsf3582/3583aasb can range from 2.67 v to 3.3 v. the th50vsf3582/3583aasb is available in a 69-pin bga package, making it suitable for a variety of design applications. features ? power supply voltage v ccs = 2.67 v~3.3 v v ccf = 2.67 v~3.3 v ? data retention supply voltage v ccs = 1.5 v~3.3 v ? current consumption operating: 45 ma maximum (cmos level) standby: 10 a maximum (sram cmos level) standby: 10 a maximum (flash) ? block erase architecture for flash memory 8 8 kbytes 63 64 kbytes ? organization ciof cios flash memory sram v cc v cc 2,097,152 words of 16 bits 524,288 words of 16 bits v cc v ss 2,097,152 words of 16 bits 1,048,576 words of 8 bits v ss v ss 4,194,304 words of 8 bits 1,048,576 words of 8 bits pin assignment (top view) pin names ? case: ciof = v cc , cios = v cc ( 16, 16) 1 2 3 4 5 6 7 8 9 10 a nc nc b nc nc c nc a7 lb /acc wp we a8 a11 d a3 a6 ub reset ce2s a19 a12 a15 e a2 a5 a18 by / ry a20 a9 a13 nc f nc a1 a4 a17 a10 a14 nc nc g nc a0 v ss dq1 dq6 du a16 nc h cef oe dq9 dq3 dq4 dq13 dq15 ciof j s 1 ce dq0 dq10 v ccf v ccs dq12 dq7 v ss k dq8 dq2 dq11 cios dq5 dq14 l nc nc m nc nc a0~a21 address inputs a12s a12 input for sram a12f a12 input for flash memory sa a18 input for sram dq0~dq15 data inputs/outputs s 1 ce , ce2s chip enable inputs for sram cef chip enable input for flash memory oe output enable input we write enable input lb , ub data byte control input by / ry ready/busy output reset hardware reset input /acc wp write protect/program acceleration input cios word enable input for sram ciof word enable input for flash memory v ccs power supply for sram v ccf power supply for flash memory v ss ground nc not connected du don?t use ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in g eneral can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of th e buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, a nd to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury o r damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in th e most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handlin g guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction o r failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energ y control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion cont rol instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this docume n t shall be made at the customer?s own risk. 000707 eba2
th50vsf3582/3583aasb 2001-06-08 2/50 pin assignment (top view) ? case: ciof = v cc , cios = v ss ( 16, 8) 1 2 3 4 5 6 7 8 9 10 a nc nc b nc nc c nc a7 du /acc wp we a8 a11 d a3 a6 du reset ce2s a19 a12 a15 e a2 a5 a18 by / ry a20 a9 a13 nc f nc a1 a4 a17 a10 a14 nc nc g nc a0 v ss dq1 dq6 sa a16 nc h cef oe dq9 dq3 dq4 dq13 dq15 ciof j s 1 ce dq0 dq10 v ccf v ccs dq12 dq7 v ss k dq8 dq2 dq11 cios dq5 dq14 l nc nc m nc nc ? case: ciof = v ss , cios = v ss ( 8, 8) 1 2 3 4 5 6 7 8 9 10 a nc nc b nc nc c nc a7 du /acc wp we a8 a11 d a3 a6 du reset ce2s a20 a13 a16 e a2 a5 a19 by / ry a21 a9 a14 nc f nc a1 a4 a18 a10 a15 nc nc g nc a0 v ss dq1 dq6 a12s a17 nc h cef oe du dq3 dq4 du a12f ciof j s 1 ce dq0 du v ccf v ccs du dq7 v ss k du dq2 du cios dq5 du l nc nc m nc nc note: a12f and a12s should be wired and used as a12 pin. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d b y toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from i ts use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation o r others. ? the information contained herein is subject to change without notice. 000707 eba2
th50vsf3582/3583aasb 2001-06-08 3/50 block diagram mode selection operation mode cef s 1 ce ce2s oe we reset ub lb /acc wp dq0~dq7 dq8~dq15 l h x l h h x x x d out d out flash read l x l l h h x x x d out d out h l h l h h l l x d out d out h l h l h h h l x d out hi-z sram read h l h l h h l h x hi-z d out l h x h l h x x x d in d in flash write l x l h l h x x x d in d in h l h x l h l l x d in d in h l h x l h h l x d in hi-z sram write h l h x l h l h x hi-z d in x h x h h x x x x hi-z hi-z flash output disable x x l h h x x x x hi-z hi-z h x x h h x x x x hi-z hi-z sram output disable h x x x x x h h x hi-z hi-z flash standby h x x x x h x x x s s flash hardware reset / standby x x x x x l x x x s s x h x x x x x x x f f sram standby x x l x x x x x x f f notes: l = v il ; h = v ih ; x = v ih or v il f : depends on flash memory operation mode. s : depends on sram operation mode. when cios = v cc and ciof = v cc , word mode is selected for both sram and flash memory. does not apply when cef = s 1 ce = v il and ce2s = v ih at the same time. 8-mbit sram memory 32-mbit flash memory dq0~dq15 a0~a21 a0~a18 v ccf v ss v ccs we oe ce2s cef a0~a21 reset by / ry s 1 ce sa v ss dq0~dq15 (dq0~dq7) dq0~dq15 (dq0~dq7) ciof ub lb cios /acc wp
th50vsf3582/3583aasb 2001-06-08 4/50 id code table type a20~a12 a6 a1 a0 code (hex) (1) manufacturer code * l l l 0098h th50vsf3582aasb * l l h 009ah device code TH50VSF3583AASB * l l h 009ch verify block protect ba (2) l h l data (3) note: * = v ih or v il l = v il h = v ih (1) dq8~dq15 are hi-z in byte mode (2) ba: block address (3) 0001h: protected block 0000h: unprotected block
th50vsf3582/3583aasb 2001-06-08 5/50 command sequences first bus write cycle second bus write cycle third bus write cycle fourth bus write cycle fifth bus write cycle sixth bus write cycle command sequence bus write cycles req?d addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxh f0h word 555h 2aah 555h read/reset byte 3 aaah aah 555h 55h aaah f0h ra (1) rd (2) word 555h 2aah bk (3) + 555h id read byte 3 aaah aah 555h 55h bk (3) + aaah 90h ia (4) id (5) word 555h 2aah 555h auto-program byte 4 aaah aah 555h 55h aaah a0h pa (6) pd (7) program suspend 1 bk (3) b0h program resume 1 bk (3) 30h word 555h 2aah 555h 555h 2aah 555h auto chip erase byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h aaah 10h word 555h 2aah 555h 555h 2aah auto block erase byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h ba (8) 30h block erase suspend 1 bk (3) b0h block erase resume 1 bk (3) 30h block protect 4 xxxh 60h bpa (9) 60h xxxh 40h bpa (9) bpd (10) word 555h 2aah bk (3) + 555h verify block protect byte 3 aaah aah 555h 55h bk (3) + aaah 90h bpa (9) bpd (10) word 555h 2aah 555h fast program set byte 3 aaah aah 555h 55h aaah 20h fast program 2 xxxh a0h pa (6) pd (7) fast program reset 2 xxxh 90h xxxh f0h (13) word 555h 2aah 555h hidden rom mode entry byte 3 aaah aah 555h 55h aaah 88h word 555h 2aah 555h hidden rom program byte 4 aaah aah 555h 55h aaah a0h pa (6) pd (7) word 555h 2aah 555h 555h 2aah hidden rom erase byte 6 aaah aah 555h 55h aaah 80h aaah aah 555h 55h ba (8) 30h word 555h 2aah 555h hidden rom mode exit byte 4 aaah aah 555h 55h aaah 90h xxxh 00h word bk (3) + 55h query command byte 2 bk (3) + aah 98h ca (11) cd (12) note: the system should generate the following address patterns: word mode: 555h or 2aah to addresses a10~a0 byte mode: aaah or 555h to addresses a10~a0, a12f ? dq8~dq15 are ignored in word mode. (1) ra: read address (2) rd: read data (3) bk: bank address = a20~a15 (4) ia: bank address and id read address (a6, a1, a0) bank address = a20~a15 manufacturer code = (0, 0, 0) device code = (0, 0, 1) (5) id: id data 0098h - manufacturer code 009ah - device code (th50vsf3582aasb) 009ch - device code (TH50VSF3583AASB) 0001h - protected block ? byte mode when v il is inputted to ciof, and addresses are a21~a0 ? write mode when v ih is inputted to ciof, and addresses are a20~a0 ? valid addresses are a10~a0 when a command is entered. (6) pa: program address (7) pd: program data (8) ba: block address = a20~a12 (9) bpa: block address and id read address (a6, a1, a0) block address = a20~a12 id read address = (0, 1, 0) (10) bpd: verify data (11) ca: cfi address (12) cd: cfi data (13) f0h: 00h is valid too
th50vsf3582/3583aasb 2001-06-08 6/50 block erase address tables th50vsf3582aasb (top boot block) block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba0 l l l l l l * * * 000000h~00ffffh 000000h~007fffh ba1 l l l l l h * * * 010000h~01ffffh 008000h~00ffffh ba2 l l l l h l * * * 020000h~02ffffh 010000h~017fffh ba3 l l l l h h * * * 030000h~03ffffh 018000h~01ffffh ba4 l l l h l l * * * 040000h~04ffffh 020000h~027fffh ba5 l l l h l h * * * 050000h~05ffffh 028000h~02ffffh ba6 l l l h h l * * * 060000h~06ffffh 030000h~037fffh bk0 ba7 l l l h h h * * * 070000h~07ffffh 038000h~03ffffh ba8 l l h l l l * * * 080000h~08ffffh 040000h~047fffh ba9 l l h l l h * * * 090000h~09ffffh 048000h~04ffffh ba10 l l h l h l * * * 0a0000h~0affffh 050000h~057fffh ba11 l l h l h h * * * 0b0000h~0bffffh 058000h~05ffffh ba12 l l h h l l * * * 0c0000h~0cffffh 060000h~067fffh ba13 l l h h l h * * * 0d0000h~0dffffh 068000h~06ffffh ba14 l l h h h l * * * 0e0000h~0effffh 070000h~077fffh bk1 ba15 l l h h h h * * * 0f0000h~0fffffh 078000h~07ffffh ba16 l h l l l l * * * 100000h~10ffffh 080000h~087fffh ba17 l h l l l h * * * 110000h~11ffffh 088000h~08ffffh ba18 l h l l h l * * * 120000h~12ffffh 090000h~097fffh ba19 l h l l h h * * * 130000h~13ffffh 098000h~09ffffh ba20 l h l h l l * * * 140000h~14ffffh 0a0000h~0a7fffh ba21 l h l h l h * * * 150000h~15ffffh 0a8000h~0affffh ba22 l h l h h l * * * 160000h~16ffffh 0b0000h~0b7fffh bk2 ba23 l h l h h h * * * 170000h~17ffffh 0b8000h~0bffffh ba24 l h h l l l * * * 180000h~18ffffh 0c0000h~0c7fffh ba25 l h h l l h * * * 190000h~19ffffh 0c8000h~0cffffh ba26 l h h l h l * * * 1a0000h~1affffh 0d0000h~0d7fffh ba27 l h h l h h * * * 1b0000h~1bffffh 0d8000h~0dffffh ba28 l h h h l l * * * 1c0000h~1cffffh 0e0000h~0e7fffh ba29 l h h h l h * * * 1d0000h~1dffffh 0e8000h~0effffh ba30 l h h h h l * * * 1e0000h~1effffh 0f0000h~0f7fffh bk3 ba31 l h h h h h * * * 1f0000h~1fffffh 0f8000h~0fffffh
th50vsf3582/3583aasb 2001-06-08 7/50 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba32 h l l l l l * * * 200000h~20ffffh 100000h~107fffh ba33 h l l l l h * * * 210000h~21ffffh 108000h~10ffffh ba34 h l l l h l * * * 220000h~22ffffh 110000h~117fffh ba35 h l l l h h * * * 230000h~23ffffh 118000h~11ffffh ba36 h l l h l l * * * 240000h~24ffffh 120000h~127fffh ba37 h l l h l h * * * 250000h~25ffffh 128000h~12ffffh ba38 h l l h h l * * * 260000h~26ffffh 130000h~137fffh bk4 ba39 h l l h h h * * * 270000h~27ffffh 138000h~13ffffh ba40 h l h l l l * * * 280000h~28ffffh 140000h~147fffh ba41 h l h l l h * * * 290000h~29ffffh 148000h~14ffffh ba42 h l h l h l * * * 2a0000h~2affffh 150000h~157fffh ba43 h l h l h h * * * 2b0000h~2bffffh 158000h~15ffffh ba44 h l h h l l * * * 2c0000h~2cffffh 160000h~167fffh ba45 h l h h l h * * * 2d0000h~2dffffh 168000h~16ffffh ba46 h l h h h l * * * 2e0000h~2effffh 170000h~177fffh bk5 ba47 h l h h h h * * * 2f0000h~2fffffh 178000h~17ffffh ba48 h h l l l l * * * 300000h~30ffffh 180000h~187fffh ba49 h h l l l h * * * 310000h~31ffffh 188000h~18ffffh ba50 h h l l h l * * * 320000h~32ffffh 190000h~197fffh ba51 h h l l h h * * * 330000h~33ffffh 198000h~19ffffh ba52 h h l h l l * * * 340000h~34ffffh 1a0000h~1a7fffh ba53 h h l h l h * * * 350000h~35ffffh 1a8000h~1affffh ba54 h h l h h l * * * 360000h~36ffffh 1b0000h~1b7fffh bk6 ba55 h h l h h h * * * 370000h~37ffffh 1b8000h~1bffffh ba56 h h h l l l * * * 380000h~38ffffh 1c0000h~1c7fffh ba57 h h h l l h * * * 390000h~39ffffh 1c8000h~1cffffh ba58 h h h l h l * * * 3a0000h~3affffh 1d0000h~1d7fffh ba59 h h h l h h * * * 3b0000h~3bffffh 1d8000h~1dffffh ba60 h h h h l l * * * 3c0000h~3cffffh 1e0000h~1e7fffh ba61 h h h h l h * * * 3d0000h~3dffffh 1e8000h~1effffh bk7 ba62 h h h h h l * * * 3e0000h~3effffh 1f0000h~1f7fffh
th50vsf3582/3583aasb 2001-06-08 8/50 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba63 h h h h h h l l l 3f0000h~3f1fffh 1f8000h~1f8fffh ba64 h h h h h h l l h 3f2000h~3f3fffh 1f9000h~1f9fffh ba65 h h h h h h l h l 3f4000h~3f5fffh 1fa000h~1fafffh ba66 h h h h h h l h h 3f6000h~3f7fffh 1fb000h~1fbfffh ba67 h h h h h h h l l 3f8000h~3f9fffh 1fc000h~1fcfffh ba68 h h h h h h h l h 3fa000h~3fbfffh 1fd000h~1fdfffh ba69 h h h h h h h h l 3fc000h~3fdfffh 1fe000h~1fefffh bk8 ba70 h h h h h h h h h 3fe000h~3fffffh 1ff000h~1fffffh
th50vsf3582/3583aasb 2001-06-08 9/50 TH50VSF3583AASB (bottom boot block) block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba0 l l l l l l l l l 000000h~001fffh 000000h~000fffh ba1 l l l l l l l l h 002000h~003fffh 001000h~001fffh ba2 l l l l l l l h l 004000h~005fffh 002000h~002fffh ba3 l l l l l l l h h 006000h~007fffh 003000h~003fffh ba4 l l l l l l h l l 008000h~009fffh 004000h~004fffh ba5 l l l l l l h l h 00a000h~00bfffh 005000h~005fffh ba6 l l l l l l h h l 00c000h~00dfffh 006000h~006fffh bk0 ba7 l l l l l l h h h 00e000h~00ffffh 007000h~007fffh ba8 l l l l l h * * * 010000h~01ffffh 008000h~00ffffh ba9 l l l l h l * * * 020000h~02ffffh 010000h~017fffh ba10 l l l l h h * * * 030000h~03ffffh 018000h~01ffffh ba11 l l l h l l * * * 040000h~04ffffh 020000h~027fffh ba12 l l l h l h * * * 050000h~05ffffh 028000h~02ffffh ba13 l l l h h l * * * 060000h~06ffffh 030000h~037fffh bk1 ba14 l l l h h h * * * 070000h~07ffffh 038000h~03ffffh ba15 l l h l l l * * * 080000h~08ffffh 040000h~047fffh ba16 l l h l l h * * * 090000h~09ffffh 048000h~04ffffh ba17 l l h l h l * * * 0a0000h~0affffh 050000h~057fffh ba18 l l h l h h * * * 0b0000h~0bffffh 058000h~05ffffh ba19 l l h h l l * * * 0c0000h~0cffffh 060000h~067fffh ba20 l l h h l h * * * 0d0000h~0dffffh 068000h~06ffffh ba21 l l h h h l * * * 0e0000h~0effffh 070000h~077fffh bk2 ba22 l l h h h h * * * 0f0000h~0fffffh 078000h~07ffffh ba23 l h l l l l * * * 100000h~10ffffh 080000h~087fffh ba24 l h l l l h * * * 110000h~11ffffh 088000h~08ffffh ba25 l h l l h l * * * 120000h~12ffffh 090000h~097fffh ba26 l h l l h h * * * 130000h~13ffffh 098000h~09ffffh ba27 l h l h l l * * * 140000h~14ffffh 0a0000h~0a7fffh ba28 l h l h l h * * * 150000h~15ffffh 0a8000h~0affffh ba29 l h l h h l * * * 160000h~16ffffh 0b0000h~0b7fffh bk3 ba30 l h l h h h * * * 170000h~17ffffh 0b8000h~0bffffh
th50vsf3582/3583aasb 2001-06-08 10/50 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba31 l h h l l l * * * 180000h~18ffffh 0c0000h~0c7fffh ba32 l h h l l h * * * 190000h~19ffffh 0c8000h~0cffffh ba33 l h h l h l * * * 1a0000h~1affffh 0d0000h~0d7fffh ba34 l h h l h h * * * 1b0000h~1bffffh 0d8000h~0dffffh ba35 l h h h l l * * * 1c0000h~1cffffh 0e0000h~0e7fffh ba36 l h h h l h * * * 1d0000h~1dffffh 0e8000h~0effffh ba37 l h h h h l * * * 1e0000h~1effffh 0f0000h~0f7fffh bk4 ba38 l h h h h h * * * 1f0000h~1fffffh 0f8000h~0fffffh ba39 h l l l l l * * * 200000h~20ffffh 100000h~107fffh ba40 h l l l l h * * * 210000h~21ffffh 108000h~10ffffh ba41 h l l l h l * * * 220000h~22ffffh 110000h~117fffh ba42 h l l l h h * * * 230000h~23ffffh 118000h~11ffffh ba43 h l l h l l * * * 240000h~24ffffh 120000h~127fffh ba44 h l l h l h * * * 250000h~25ffffh 128000h~12ffffh ba45 h l l h h l * * * 260000h~26ffffh 130000h~137fffh bk5 ba46 h l l h h h * * * 270000h~27ffffh 138000h~13ffffh ba47 h l h l l l * * * 280000h~28ffffh 140000h~147fffh ba48 h l h l l h * * * 290000h~29ffffh 148000h~14ffffh ba49 h l h l h l * * * 2a0000h~2affffh 150000h~157fffh ba50 h l h l h h * * * 2b0000h~2bffffh 158000h~15ffffh ba51 h l h h l l * * * 2c0000h~2cffffh 160000h~167fffh ba52 h l h h l h * * * 2d0000h~2dffffh 168000h~16ffffh ba53 h l h h h l * * * 2e0000h~2effffh 170000h~177fffh bk6 ba54 h l h h h h * * * 2f0000h~2fffffh 178000h~17ffffh ba55 h h l l l l * * * 300000h~30ffffh 180000h~187fffh ba56 h h l l l h * * * 310000h~31ffffh 188000h~18ffffh ba57 h h l l h l * * * 320000h~32ffffh 190000h~197fffh ba58 h h l l h h * * * 330000h~33ffffh 198000h~19ffffh ba59 h h l h l l * * * 340000h~34ffffh 1a0000h~1a7fffh ba60 h h l h l h * * * 350000h~35ffffh 1a8000h~1affffh ba61 h h l h h l * * * 360000h~36ffffh 1b0000h~1b7fffh bk7 ba62 h h l h h h * * * 370000h~37ffffh 1b8000h~1bffffh
th50vsf3582/3583aasb 2001-06-08 11/50 block address bank address address range bank # block # a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode ba63 h h h l l l * * * 380000h~38ffffh 1c0000h~1c7fffh ba64 h h h l l h * * * 390000h~39ffffh 1c8000h~1cffffh ba65 h h h l h l * * * 3a0000h~3affffh 1d0000h~1d7fffh ba66 h h h l h h * * * 3b0000h~3bffffh 1d8000h~1dffffh ba67 h h h h l l * * * 3c0000h~3cffffh 1e0000h~1e7fffh ba68 h h h h l h * * * 3d0000h~3dffffh 1e8000h~1effffh ba69 h h h h h l * * * 3e0000h~3effffh 1f0000h~1f7fffh bk8 ba70 h h h h h h * * * 3f0000h~3fffffh 1f8000h~1fffffh
th50vsf3582/3583aasb 2001-06-08 12/50 block size table th50vsf3582aasb (top boot block) block size bank size block # byte mode word mode bank # byte mode word mode block count ba0~ba7 64 kbytes 32 kwords bk0 512 kbytes 256 kwords 8 ba8~ba15 64 kbytes 32 kwords bk1 512 kbytes 256 kwords 8 ba16~ba23 64 kbytes 32 kwords bk2 512 kbytes 256 kwords 8 ba24~ba31 64 kbytes 32 kwords bk3 512 kbytes 256 kwords 8 ba32~ba39 64 kbytes 32 kwords bk4 512 kbytes 256 kwords 8 ba40~ba47 64 kbytes 32 kwords bk5 512 kbytes 256 kwords 8 ba48~ba55 64 kbytes 32 kwords bk6 512 kbytes 256 kwords 8 ba56~ba62 64 kbytes 32 kwords bk7 448 kbytes 224 kwords 7 ba63~ba70 8 kbytes 4 kwords bk8 64 kbytes 32 kwords 8 TH50VSF3583AASB (bottom boot block) block size bank size block # byte mode word mode bank # byte mode word mode block count ba0~ba7 8 kbytes 4 kwords bk0 64 kbytes 32 kwords 8 ba8~ba14 64 kbytes 32 kwords bk1 448 kbytes 224 kwords 7 ba15~ba22 64 kbytes 32 kwords bk2 512 kbytes 256 kwords 8 ba23~ba30 64 kbytes 32 kwords bk3 512 kbytes 256 kwords 8 ba31~ba38 64 kbytes 32 kwords bk4 512 kbytes 256 kwords 8 ba39~ba46 64 kbytes 32 kwords bk5 512 kbytes 256 kwords 8 ba47~ba54 64 kbytes 32 kwords bk6 512 kbytes 256 kwords 8 ba55~ba62 64 kbytes 32 kwords bk7 512 kbytes 256 kwords 8 ba63~ba70 64 kbytes 32 kwords bk8 512 kbytes 256 kwords 8
th50vsf3582/3583aasb 2001-06-08 13/50 absolute maximum ratings symbol parameter range unit v cc v ccs /v ccf supply voltage ? 0.3~4.2 v v in input voltage (1) ? 0.3~4.2 ? v v dq input/output voltage ? 0.5~v cc + 0.5 ( 4.2) v t opr operating temperature ? 30~85 c p d power dissipation 0.6 w t solder soldering temperature (10 s) 260 c i oshort output short circuit current (2) 100 ma n ew erase/program cycling capability 100,000 cycle t stg storage temperature ? 55~125 c (1) ? 2.0 v for pulse width 20 ns (2) output shorted for no more than one second. no more than one output shorted at a time hardware status flags status dq7 dq6 dq5 dq3 dq2 by / ry auto programming 7 dq toggle 0 0 1 0 read in program suspend (1) data data data data data hi-z selected (2) 0 toggle 0 0 toggle 0 erase hold time non-selected (3) 0 toggle 0 0 1 0 selected 0 toggle 0 1 toggle 0 in auto- erase auto-erase non-selected 0 toggle 0 1 1 0 selected 1 1 0 0 toggle hi-z read non-selected data data data data data hi-z selected 7 dq toggle 0 0 toggle 0 in progress in erase suspend programming non-selected 7 dq toggle 0 0 1 0 auto programming 7 dq toggle 1 0 1 0 auto-erase 0 toggle 1 1 n/a 0 time limit exceeded programming in erase suspend 7 dq toggle 1 0 n/a 0 notes: dq outputs cell data and by / ry to high impedence when the operation has completed. dq0 and dq1 pins are reserved for futyre use. dq0, dq1 and dq4 output 0. (1) data output from an address to which write is being performed are undefined. (2) output when the block address selected for auto block erase is specified and data is read from there. during auto chip erase, all blocks are selected. (3) output when a block address not selected for auto block erase of same bank as selected block is specified and data is read from there.
th50vsf3582/3583aasb 2001-06-08 14/50 recommended dc operating conditions (ta = = = = -30~85c) symbol parameter min typ. max unit v ccs /v ccf power supply voltage 2.67 ? 3.3 v ih input high-level voltage 2.2 ? v cc + 0.3 v il input low-level voltage ? 0.3 (1) ? v cc 0.2 v dh data retention voltage for sram 1.5 ? 3.3 v lko flash low-lock voltage 2.3 ? 2.5 v acc high voltage for /acc wp 8.5 ? 9.5 v id high voltage for reset 11.4 ? 12.6 v (1) ? 2.0 v for pulse width 20 ns capacitance (ta = = = = 25c, f = = = = 1 mhz) symbol parameter condition min typ. max unit c in input capacitance v in = gnd ? ? 15 pf c out output capacitance v out = gnd ? ? 20 pf note: these parameters are sampled periodically and are not tested for every device.
th50vsf3582/3583aasb 2001-06-08 15/50 dc characteristics (ta = = = = -30~85c, v ccs /v ccf = = = = 2.67 v~3.3 v) symbol parameter condition min typ. max unit i il input leakage current v in = 0 v~v cc ? ? 1 a i ilw input leakage current ( /acc wp pin) 0 v v in v cc ? ? 10 a i soh sram output high current v oh = v ccs ? 0.5 v ? 0.5 ? ? ma i sol sram output low current v ol = 0.4 v 2.1 ? ? ma i foh1 flash output high current (ttl) v oh = 2.4 v ? 0.4 ? ? ma v oh = v ccf 0.85 ? 2.5 ? ? ma i foh2 flash output high current (cmos) v oh = v ccf ? 0.4 v ? 100 ? ? a i fol flash output low current v ol = 0.4 v 4 ? ? ma i lo output leakage current v out = 0 v~v cc , oe = v ih ? ? 1 a i cco1 flash average read current cef = v il , oe = v ih , i out = 0 ma, t cycle = t rc (min) ? ? 30 ma i cco2 flash average program/ erase current cef = v il , oe = v ih , i out = 0 ma ? ? 15 ma t cycle = t rc ? ? 50 i cco3 s 1 ce = v il , ce2s = v ih , oe = v ih , i out = 0 ma t cycle = 1 mhz ? ? 10 ma t cycle = t rc ? ? 45 i cco4 sram average operating current s 1 ce = 0.2 v, oe = v ccs ? 0.2 v, ce2s = v ccs ? 0.2 v, i out = 0 ma t cycle = 1 mhz ? ? 5 ma i cco5 flash average read-while-program current v in = v ih /v il , i out = 0 ma, t cycle = t rc (min) ? ? 45 ma i cco6 flash average read-while- erase current v in = v ih /v il , i out = 0 ma, t cycle = t rc (min) ? ? 45 ma i cco7 flash average program-while- erase-suspend current v in = v ih /v il , i out = 0 ma ? ? 15 ma i ccs1 flash standby current cef = reset = v ccf or reset = v ss ? ? 10 a i ccs2 flash standby current (automatic sleep mode (1) ) v ih = v ccf or v il = v ss ? ? 10 a i ccs3 s 1 ce = v ih or ce2s = v il ? ? 2 ma ta = 25c ? ? 1 v ccs = 3.3 v ta = ? 30~85c ? ? 10 ta = 25c ? 0.01 0.5 ta = ? 30~40c ? ? 1 i ccs4 sram standby current s 1 ce = v ccs ? 0.2 v or ce2s = 0.2 v (2) v ccs = 3.0 v ta = ? 30~85c ? ? 5 a i acc high voltage input current for /acc wp 8.5 v v acc 9.5 v ? ? 20 ma (1) the device is going to automatic sleep mode, when address remain steady during 150 ns. (2) in standby mode, with s 1 ce v ccs ? 0.2 v, these limits are guaranteed when ce2s v ccs ? 0.2 v or ce2s 0.2 v and cios v ccs ? 0.2 v or cios 0.2 v.
th50vsf3582/3583aasb 2001-06-08 16/50 ac characteristics (sram) (ta = = = = -40~85c, v ccs = = = = 2.7 v~3.6 v) read cycle symbol parameter min max unit t rc read cycle time 70 ? t acc address access time ? 70 t co1 chip enable ( s 1 ce ) access time ? 70 t co2 chip enable (ce2s) access time ? 70 t oe output enable access time ? 35 t ba data byte control access time ? 35 t coe chip enable low to output active 5 ? t oee output enable low to output active 0 ? t be data byte control low to output active 0 ? t od chip enable high to output hi-z ? 30 t odo output enable high to output hi-z ? 30 t bd data byte control high to output hi-z ? 30 t oh output data hold time 10 ? t ccr ce recovery time 0 ? ns write cycle symbol parameter min max unit t wc write cycle time 70 ? t wp write pulse width 50 ? t cw chip enable to end of write 60 ? t bw data byte control to end of write 50 ? t as address set-up time 0 ? t wr write recovery time 0 ? t odw we low to output hi-z ? 30 t oew we high to output active 0 ? t ds data set-up time 30 ? t dh data hold time 0 ? ns ac test conditions parameter values input pulse level 0.4 v, 2.4 v input pulse rise and fall time (10%~90%) 5 ns timing measurement reference level (input) v ccs 0.5 timing measurement reference level (output) v ccs 0.5 output load c l (100 pf) + 1 ttl gate
th50vsf3582/3583aasb 2001-06-08 17/50 ac characteristics (flash memory) read cycle load capacitance 30pf 100pf symbol parameter min max min max unit t rc read cycle time 70 ? ? 80 ns t acc address access time ? 70 ? 80 ns t ce cef access time ? 70 ? 80 ns t oe oe access time ? 30 ? 35 ns t cee cef to output low-z 0 ? 0 ? ns t oee oe to output low-z 0 ? 0 ? ns t oeh oe hold time 0 ? 0 ? ns t oh output data hold time 0 ? 0 ? ns t df1 cef to output hi-z ? 30 ? 25 ns t df2 oe to output hi-z ? 20 ? 25 ns block protect symbol parameter min max unit t vps v id set-up time 4 ? s t cesp cef set-up time 4 ? s t vph oe hold time 4 ? s t pplh we low-level hold time 100 ? s program and erase characteristics symbol parameter min max unit auto-program time (byte mode) 8 * 300 s t ppw auto-program time (word mode) 11 * 300 s t pcew auto chip erase time 50 * 710 s t pbew auto block erase time 0.7 * 10 s t ew erase/program cycle 10 5 ? cycles * : typ.
th50vsf3582/3583aasb 2001-06-08 18/50 command write/program/erase cycle load capacitance 30pf 100pf symbol parameter min max min max unit t cmd command write cycle time 70 ? 80 ? ns t as address set-up time / byte set-up time 0 ? 0 ? ns t ah address hold time / byte hold time 40 ? 40 ? ns t ahw address hold time from we high level 20 ? 20 ? ns t ds data set-up time 40 ? 40 ? ns t dh data hold time 0 ? 0 ? ns t welh we low-level hold time ( we control) 40 ? 40 ? ns t wehh we high-level hold time ( we control) 20 ? 20 ? ns t ces cef set-up time to we active ( we control) 0 ? 0 ? ns t ceh cef hold time from we high level ( we control) 0 ? 0 ? ns t celh cef low-level hold time ( cef control) 40 ? 40 ? ns t cehh cef high-level hold time ( cef control) 20 ? 20 ? ns t wes we set-up time to cef active ( cef control) 0 ? 0 ? ns t weh we hold time from cef high level ( cef control) 0 ? 0 ? ns t oes oe set-up time 0 ? 0 ? ns t oehp oe hold time (toggle, data polling) 90 ? 90 ? ns t oeht oe high-level hold time (toggle) 20 ? 20 ? ns t beh erase hold time 50 ? 50 ? s t vcs v ccf set-up time 500 ? 500 ? s t busy program/erase valid to by / ry delay ? 90 ? 90 ns t rp reset low-level hold time 500 ? 500 ? ns t ready reset low-level to read mode ? 20 ? 20 s t rb by / ry recovery time 0 ? 0 ? ns t rh reset recovery time 50 ? 50 ? ns t cebts cef set-up time byte transition 5 ? 5 ? ns t susp program suspend command to suspend mode ? 1.5 ? 1.5 s t resp program resume command to program mode ? 1 ? 1 s t suse erase suspend command to suspend mode ? 15 ? 15 s t rese erase resume command to erase mode ? 1 ? 1 s
th50vsf3582/3583aasb 2001-06-08 19/50 simultaneous read/write operation the th50vsf3582/3583aasb features a simultaneous read/write operation. the simultaneous read/write operation enables the device to simultaneously write data to or erase data from a bank while the device reads data from another bank. the th50vsf3582/3583aasb has a total of nine banks: 0.5 mbits 1 bank, 3.5 mbits 1 bank, and 4 mbits 7 banks. banks are switched using bank addresses (a20 to a15). for bank blocks and addresses, refer to the block address table and block size table. the simultaneous read/write operation cannot perform multiple operations in a bank. the table below shows the operating modes in which simultaneous operation can be performed. note that during auto program execution or auto block erase operation, the simultaneous read/write operation cannot read data from addresses which are not selected for operation in the same bank. data from such addresses can be read using the program suspend or erase suspend function. simultaneous read/write operation one bank status other bank status read mode id read mode (1) auto program mode fast program mode (2) program suspend mode auto block erase mode auto multiple block erase mode (3) erase suspend mode program suspend while erase suspend cfi mode read mode (1) command mode only is valid. (2) includes when acceleration mode is in use. (3) if the selected bank exists in all banks, simultaneous operation is not supported. operating modes in addition to read, write, and erase modes, the th50vsf3582/3583aasb features many functions including block protect and data polling. when using the device, reference the timing charts and flow charts together with the description below. read mode to read data from the memory cell array, set the device to read mode. in read mode, the device can perform high-speed random access as asynchronous rom. the device is automatically set to read mode immediately after power on or after completion of automatic operation. a software reset releases id read mode and the lock state when automatic operation ends abnormally, and sets to read mode. a hardware reset terminates operation of the device and resets to read mode. when reading the data without changing the address immediately after power on, either input a hardware reset or change cef from h to l.
th50vsf3582/3583aasb 2001-06-08 20/50 id read mode id read mode is used to read the device maker code and device code. the mode is useful for eprom programmers to automatically identify the device type. in this method, simultaneous operation can be performed. inputting an id read command sets the specified bank to id read mode. banks are specified by inputting the bank address (bk) in the third bus write cycle of the command cycle. to read an id code, the bank address as well as the id read address must be specified. from address bk + 00 the maker code is output; from address bk + 01 the device code is output. from other banks, data are output from the memory cells. inputting a reset command releases id read mode and returns the device to read mode. access time in id read mode is the same as that in read mode. for the codes, see the id code table. standby mode there are two methods of entering standby mode. (1) control using cef and reset when the device is in read mode, input v dd 0.3 v to cef and reset . the device enters standby mode and the current becomes standby current (i ccs1 ). however, if the device is in simultaneous operation, the device does not enter standby mode but causes the operating current to flow. (2) control using only reset when the device is in read mode, input v ss 0.3 v to reset . the device enters standby mode and the current becomes standby current (i ccs1 ). even if the device is in simultaneous operation, this method can terminate the current operation and set the device to standby mode. this is a hardware reset, described later. in standby mode, dq is put in high-impedance state. auto sleep mode function which suppresses power dissipation during read. when address input does not change for 150 ns or longer, the device automatically enters sleep mode and the current becomes standby current (i ccs1 ). however, if the device is in simultaneous operation, the device does not enter standby mode but causes the operating current to flow. because the output data are latched, data are output in sleep mode. when the address is changed, sleep mode is automatically released, outputting data from the changed address. output disable mode inputting v ih to oe disables output from the device, setting dq to high-impedance.
th50vsf3582/3583aasb 2001-06-08 21/50 command write the th50vsf3582/3583aasb utilizes the jedec command control standard for a single power supply e 2 prom. a command is executed by inputting an address and data into the command register. the command is written by inputting a pulse to we with cef = v il and oe = v ih ( we control). the command can also be written by inputting a pulse to cef with we = v il ( cef control). the address is latched on the falling edge of either we or cef . the data is latched on the rising edge of either we or cef . dq0 to dq7 are valid for data input and dq8 to dq15 are ignored. to cancel input of the command sequence mid-way, use the reset command. the device resets the command register and enters read mode. when an undefined command is input, the command register is reset and the device enters read mode. software reset apply a software reset by inputting a read/reset command. software reset returns the device from id read or cfi mode to read mode, releases the lock state when automatic operation ends abnormally, or clears the command register. hardware reset a hardware reset initializes the device and sets it to read mode. when a pulse is input to reset for t rp , the device ends the operation in progress and enters read mode after t ready . note that if a hardware reset is applied during data overwrite such as a write or erase operation, data at that address or block become undefined. after a hardware reset the device enters read mode when reset = v ih and standby mode when reset = v il . the dq pins are high-impedance when reset = v il . the read operation sequence and input of any command are allowed after the device enters read mode. comparison with software reset and hardware reset action software reset hardware reset release id read or cfi mode valid valid clear the command resister valid valid release the lock state when automatic operation ends abnormally valid valid stop automatic operation in progress invalid valid all stops of operation other than the above, and return to read mode invalid valid /word mode ciof is used select word mode (16 bits) or byte mode (8 bits) for the th50vsf3582/3583aasb. when v ih is input to ciof, the device operates in word mode. read data or write commands using dq0 to dq15. when v il is input to ciof, read data or write commands using dq0 to dq7. a12f is used as the lowest address. dq8 to dq14 become high-impedance. byte
th50vsf3582/3583aasb 2001-06-08 22/50 auto-program mode the th50vsf3582/3583aasb can be programmed in either byte or word units. the auto program mode is set using the program command. the program address is latched on the falling edge of the we signal and data is latched on the rising edge of the fourth bus cycle (with we control). auto programming starts on the rising edge of the we signal in the fourth bus cycle. the program and program verify commands are automatically executed by the chip. the device status during programming is determined from the hardware sequence flag. to read the hardware sequence flag, specify the address to which write is being performed . during auto program execution, a command sequence for the bank on which execution is being performed cannot be received. to terminate execution, use a hardware reset. note that when the operation is terminated, data cannot be correctly written. programming of a protected block is ignored. the device enters read mode 3 s after the rising edge of the we signal in the fourth bus cycle. if an auto program operation fails, the device remains in programming state and does not automatically return to read mode. the device status can be determined from the setting of the hardware sequence flag. either a reset command or a hardware reset is necessary to return the device to read mode after a failure. if a programming operation fails, please do not try to use the block which contains the address to which data could not be programmed. the device allows the programming of memory cells from 1 to 0. the programming of memory cells from 0 to 1 will fail. at this time, execution of auto program fails. this indicates that the failure is due to the usage rather than the device. a cell must be erased to turn it from 0 to 1. fast program mode fast program is a function which enables execution of the command sequence for the auto program in two cycles. in this mode the first two cycles of the command sequence, which normally needs four cycles, are omitted. write is performed in the remaining two cycles. to execute fast program, input the fast program set command. write in this mode uses the fast program command but operation is the same at that for ordinary auto program. the status of the device can be checked using the hardware sequence flag and read operations can be performed as usual. to exit this mode, the fast program reset command must be input. when the command is input, the device returns to read mode. acceleration mode the th50vsf3582/3583aasb features acceleration mode for reducing write time. applying v acc to wp or acc automatically sets the device to acceleration mode. in acceleration mode, block protect mode changes to temporary block unprotect mode. write mode changes to fast program mode. modes are switched by the /acc wp signal; thus, there is no need for a temporary block unprotect operation or for setting or resetting fast program mode. operation of write is the same as that in auto program mode. releasing v acc to /acc wp ends acceleration mode.
th50vsf3582/3583aasb 2001-06-08 23/50 program suspend / resume mode program suspend is used to enable data read by suspending write operation. the device receives a program suspend command in write mode (including write performed during erase suspend) but ignores the command in other modes. at command input, the address of the bank on which write is being performed must be specified. after command input, the device enters program suspend read mode after t susp . during program suspend, cell data read, id read and cfi data read can be performed. when data write is suspended, the address to which write was being performed becomes undefined. id read and cfi data read are the same as usual. after completion of program suspend, to return to write mode, input a program resume command. at command input, specify the address of the bank on which write is being performed. when the id read and cfi data read functions are used, end the functions before inputting the resume command. on receiving the resume command, the device returns to write mode and resumes output of a hardware sequence flag from the bank to which data are being written. program suspend can be run in fast program or acceleration mode. however, note that when running program suspend in acceleration mode, do not release v acc . auto chip erase mode the auto chip erase mode is set using the chip erase command. the auto chip erase operation starts on the rising edge of we in the sixth bus cycle. all memory cells are automatically preprogrammed to 0, erased and verified as erased by the chip. the device status is determined from the hardware sequence flag. command inputs are ignored during an auto chip erase. the hardware reset allows interruption of an auto chip erase operation. the auto chip erase operation does not complete correctly when interrupted. hence a further erase operation is necessary. an attempt to erase a protected block is ignored. if all blocks are protected, the auto erase operation will not be executed and the device will enter read mode 100 s after the rising edge of the we signal in the sixth bus cycle. if an auto chip erase operation fails, the device remains in, erasing state and does not return to read mode. the device status is determined from the hardware sequence flag. either a reset command or a hardware reset is necessary to return the device to read mode after a failure. in this case, the block in which a failure occurred cannot be detected. either terminate device usage, or perform block erase for each block, specify the failed block, and stop using it. the host processor must take measures to prevent use of the failed block being used in the future.
th50vsf3582/3583aasb 2001-06-08 24/50 auto block / multiple block erase mode the auto block and multiple block erase modes are set using the block erase command. the block address is latched on the falling edge of the we signal in the sixth bus cycle. the block erase starts as soon as the erase hold time (t beh ) has elapsed after the rising edge of the we signal. to erase multiple blocks, repeat the 6 th bus write cycles and input the block addresses and the auto block erase command within the erase hold time (auto multiple block erase). if a command sequence other than auto block erase or erase suspend command is input during the erase hold time, the device resets the command register and enters read mode. the erase hold time is valid every we rising edge. once operation starts, all the memory cells in the block selected in the device are automatically preprogrammed to data 0, erased, and erase is verified. the device status can be determined from the setting of the hardware sequence flag. to read the hardware sequence flag, the addresses of blocks on which auto erase is being performed must be specified. when the selected blocks exit in all the banks, simultaneous operation cannot be performed. commands (except erase suspend) are ignored during a block/multiple block erase operation. the operation can be aborted by a hardware reset. the auto erase operation does not complete correctly when aborted, therefore, a further erase operation is necessary. an attempt to erase a protected block is ignored. if all the selected blocks are protected, the auto erase operation is not executed and the device returns to read mode 100 s after the rising edge of the we signal in the last bus cycle. if an auto erase operation fails, the device remains in erasing state and does not return to read mode. the device status is determined from the hardware sequence flag. either a reset command or a hardware reset is necessary to return the device to read mode after a failure. if multiple blocks are selected, the block in which a failure occurred cannot be detected. either terminate device usage, or perform block erase for each block, specify the failed block, and stop using it. the host processor must take measures to prevent use of the failed block being used in the future. erase suspend / resume mode erase suspend mode suspends auto block erase and reads data from or writes data to an unselected block. the erase suspend command is allowed during an auto block erase operation but is ignored in all other oreration modes. the erase suspend command is inhibited to input during the erase hold time. when the command is input, the address of the bank on which erase is being performed must be specified. in erase suspend mode only a read, program or resume command can be accepted. if an erase suspend command is input during an auto block erase, the device will enter erase suspend read mode after t suse . the device status (erase suspend read mode) can be verified by checking the hardware sequence flag. if data is read consecutively from the block selected for auto block erase, the dq2 output will toggle and the dq6 output will stop toggling and by / ry will be set to high-impedance. inputting a write command during an erase suspend enables a write to be performed to a block which has not been selected for the auto block erase. data is written in the usual manner. to resume the auto block erase, input an erase resume command. on input of the command, the address of the bank on which the write was being performed must be specified. on receiving an erase resume command, the device returns to the state it was in when the erase suspend command was input. if an erase suspend command is input during the erase hold time, the device will return to the state it was in at the start of the erase hold time. at this time more blocks can be specified for erasing. if an erase resume command is input during an auto block erase, erase resumes. at this time toggle output of dq6 resumes and 0 is output on by / ry .
th50vsf3582/3583aasb 2001-06-08 25/50 block protect block protection is a function to disable write and erase in block units. applying v id to reset and inputting the block protect command performs block protection. the first cycle of the command sequence is the setup command. in the second cycle, the block protect command is input, in which a block address and a1 = v ih and a0 = a6 = v il are input. at this time, the device writes to the block protector circuit, until write is complete, there must be a wait of t pplh but the device need not be controlled during this time. in the third cycle, the verify block protect command is input. this command verifies write to the block protector circuit. read is performed in the fourth cycle. if the protection operation is complete, 01h is output. if other than 01h is output, write is not complete; thus, input the block protect command again. canceling v id to reset exits this mode. temporary block unprotection the tc58vsf3580/3581aasb has a temporary block unprotection feature which disables block protection for all protected blocks. unprotection is enabled by applying v id to the reset pin. at this time, write and erase operations can be performed on all the blocks except the boot blocks protected by boot block protect. the device returns to the previous condition after v id is removed from the reset pin. that is, previously protected blocks are protected again. verify block protect the verify block protect command is used to ascertain whether a block is protected or unprotected. this mode is set by setting a0, a6 and the block address a19~a12 to v il and setting a1 to v ih . this command should be input before a read operation is performed. 0001h is output if the block is protected and 0000h is output if the block is unprotected. in byte mode dq8 to dq15 are in high-impedance state. block protection verification can also be carried out using a software command. boot block protection boot block protection temporarily protects some boot blocks using a method other than ordinary block protection. v id or a command sequence is not required. protection is performed simply by inputting v il to /acc wp . the target blocks are two of the boot blocks. the top boot block uses ba69/ba70; the bottom boot block, ba0/ba1. inputting v ih to /acc wp releases the mode. at this time, the block is protected in ordinary block protection mode.
th50vsf3582/3583aasb 2001-06-08 26/50 hidden rom area the th50vsf3582/3583aasb features a 64-kbyte hidden rom area apart from the memory cells. the area consists of one block. data read, write, and protect can be performed on the block. because protect cannot be released, once the block is protected, data in the block cannot be overwritten. the hidden rom area is located in the address space indicated in the hidden rom area address table. normally, memory cell data are accessed. to access the hidden rom area, input a hidden rom mode entry command. at this time, the device enters hidden rom mode, allowing read, write, erase, and block protect. write and erase operations are the same as auto operations except that the device is in hidden rom mode. to protect the hidden rom area, use the block protect function. operation of block protect here is the same as in normal block protect except that v ih rather than v id is input to reset . once the block is protected, protection cannot be released even using a temporary block unprotect function. use block protect carefully. note that in hidden rom mode, simultaneous operation cannot be performed. therefore, do not access areas other than the hidden rom area. to exit hidden rom mode, use the hidden rom mode exit command. the device returns to read mode. hidden rom area address table byte mode word mode type boot block architecture address range size address range size th50vsf3582aasb top boot block 3f0000h~3fffffh 64 kbytes 1f8000h~1fffffh 32 kwords TH50VSF3583AASB bottom boot block 000000h~00ffffh 64 kbytes 000000h~007fffh 32 kwords
th50vsf3582/3583aasb 2001-06-08 27/50 common flash memory interface (cfi) the th50vsf3582/3583aasb conforms to the cfi. information on device specifications and characteristics can be obtained via cfi. to read information from the device, input the query command followed by the address. in word mode, dq8 to dq15 all output 0s. to exit this mode, input the reset command. cfi code table address a6~a0 data dq15~dq0 description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ? qry ? 13h 14h 0002h 0000h primary oem command set 2: amd/fj standard type 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set 0: none exists 19h 1ah 0000h 0000h address for alternate oem extended table 1bh 0027h v dd min (write/erase) dq7~dq4: 1 v dq3~dq0: 100 mv 1ch 0036h v dd max (write/erase) dq7~dq4: 1 v dq3~dq0: 100 mv 1dh 0000h v pp min voltage 1eh 0000h v pp max voltage 1fh 0004h typical timeout per single byte/word write (2 n s) 20h 0000h typical timeout for min size buffer write (2 n s) 21h 000ah typical timeout per individual block erase (2 n ms) 22h 0000h typical timeout for full chip erase (2 n ms) 23h 0005h max timeout for byte/word write (2 n times typical) 24h 0000h max timeout for buffer write (2 n times typical) 25h 0004h max timeout per individual block erase (2 n times typical) 26h 0000h max timeout for full chip erase (2 n times typical) 27h 0016h device size (2 n byte) 28h 29h 0002h 0000h flash device interface description 2: 8/ 16 2ah 2bh 0000h 0000h max number of byte in multi-byte write (2 n )
th50vsf3582/3583aasb 2001-06-08 28/50 address a6~a0 data dq15~dq0 description 2ch 0002h number of erase block region within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information 0~15 bit: y = block number 16~31 bit: z = block size (z 256 byte) 31h 32h 33h 34h 003eh 0000h 0000h 0001h erase block region 2 information 40h 41h 42h 0050h 0052h 0049h query unique ascii string ? pri ? 43h 0031h major version number, ascii 44h 0031h minor version number, ascii 45h 0000h address sensitive unlock 0: required 1: not required 46h 0002h erase suspend 0: not supported 1: to read only 2: to read & write 47h 0001h block protect 0: not supported x: number of blocks in per group 48h 0001h block temporary unprotect 0: not supported 1: supported 49h 0004h block protect/unprotect scheme 4ah 0001h simultaneous operation 0: not supported 1: supported 4bh 0000h burst mode 0: not supported 4ch 0000h page mode 0: not supported 4dh 0085h v acc min voltage dq7~dq4: 1 v dq3~dq0: 100 mv 4eh 0095h v acc max voltage dq7~dq4: 1 v dq3~dq0: 100 mv 4fh 000xh top/bottom boot block flag 2: th50vsf3582aasb 3: TH50VSF3583AASB 50h 0001h program suspend 0: not supported 1: supported
th50vsf3582/3583aasb 2001-06-08 29/50 hardware sequence flags for flash memory the th50vsf3582/3583aasb has a hardware sequence flag which allows the device status to be determined during an auto mode operation. the output data is read out using the same timing as that used when cef = oe = v il in read mode. the by / ry output can be either high or low. the device re-enters read mode automatically after an auto mode operation has been completed successfully. the hardware sequence flag is read to determine the device status and the result of the operation is verified by comparing the read-out data with the original data. dq7 ( polling) during an auto-program or auto-erase operation, the device status can be determined using the data polling function. data polling begins on the rising edge of we in the last bus cycle. in an auto-program operation, dq7 outputs inverted data during the programming operation and outputs actual data after programming has finished. in an auto-erase operation, dq7 outputs 0 during the erase operation and 1 when the erase operation has finished. if an auto mode operation fails, dq7 simply outputs the data. when the operation has finished, the address latch is reset. data polling is asynchronous with the oe signal. dq6 (toggle bit 1) the device status can be determined by the toggle bit function during an auto program or auto erase operation. the toggle bit begins toggling on the rising edge of we in the last bus cycle. dq6 alternately outputs a 0 or a 1 for each attempt ( oe access) while cef = v il while the device is busy. when the internal operation has been completed, toggling stops and valid memory cell data can be read by subsequent reading. if the operation failed, the dq6 output toggles. dq6 toggles for around 3 s when an attempt is made to execute an auto program operation on a protected block. it then stops toggling. dq6 toggles for around 100 s when an attempt is made to execute an auto erase operation on a protected block. it then stops toggling. after toggling stops the device returns to read mode. dq5 (internal time-out) dq5 outputs a 1 when the internal timer has timed out during a program or erase operation. this indicates that the operation has not completed within the allotted time. an attempt to program 1 into a cell containing 0 will fail (see auto program mode). dq5 outputs 1 in this case. either a hardware reset or a software reset command is required to put the device into read mode. data
th50vsf3582/3583aasb 2001-06-08 30/50 dq3 (block erase timer) the block erase operation starts 50 s (erase hold time) after the rising edge of we in the last command cycle. dq3 outputs a 0 during the block erase hold time and a 1 when the erase operation starts. additional block erase commands can only be accepted during this block erase hold time. each block erase command received within this hold time resets the timer, allowing additional blocks to be marked for erasing. dq3 outputs a 1 if the program or erase operation fails. dq2 (toggle bit 2) dq2 is used to detect blocks for auto block erase or to detect whether the device is in erase suspend mode. during auto block erase, if data are continuously read from the selected block, dq2 output toggles. at this time 1 is output from non-selected blocks; thus, the selected block can be detected. when the device is in erase suspend mode, if data are continuously read from the selected block for auto block erase, dq2 output toggles. at this time, because dq6 output does not toggle, erase suspend mode can be detected. when the device is in programming mode during erase suspend, if data are read from the address to which data are being written, dq2 outputs 1. (ready / ) the th50vsf3582/3583aasb has a by / ry signal to indicate the device status to the host processor. a 0 (busy state) indicates that an auto program or auto erase operation is in progress. a 1 (ready state) indicates that the operation has finished and that the device can accept a new command. the by / ry signal outputs a 0 when an operation has failed. the by / ry signal outputs a 0 after the rising edge of we in the last command cycle. during an auto block erase operation, commands other than erase suspend are ignored. the by / ry signal outputs a 1 during an erase suspend operation. the output buffer for the by / ry pin is an open drain type circuit, allowing a wired ? or connection. a pull-up resistor needs to be inserted between v cc and the by / ry pin. by / ry busy
th50vsf3582/3583aasb 2001-06-08 31/50 data protection the th50vsf3582/3583aasb features a function which makes malfunction or data damage difficult. protection against program/erase caused by low supply voltage to prevent malfunction at power on or power down, the device does not receive commands when v ccf is below v lko . in this state, command input is ignored. if v ccf drops below v lko during auto operations, the device terminates auto program execution. in this case, auto operation is not executed again when v ccf return to recommended v ccf voltage therefore, command need to be input to execute auto operation again. when v ccf > v lko , make up countermeasure to be input accurately command in system side please. protection against malfunction caused by glitches to prevent malfunction caused by noise from the system in operation, the device does not receive pulses shorter than 3 ns(typ.) input to we , cef , or oe . however, if a glitch exceeding 3 ns(typ.) occurs and the glitch is input to the device, although rare, malfunction may occur. the device uses standard jedec commands; thus making command input difficult. it is conceivable that in an extreme case a part of a command sequence input due to system noise may occur. at this time, the device acknowledges the part of the command sequence. then, even if the proper command is input, the device does not operate. to avoid this, before command input, clear the command register. in an environment where system noise occurs easily, toshiba recommends input of a software or hardware reset before command input. protection against malfunction at power-on to prevent damage to data caused by sudden noise at power on, when power is turned on with we = cef = v il and oe = v il , the device does not latch the command at the first rising edge of we or cef . the device automatically resets the command register and enters read mode.
th50vsf3582/3583aasb 2001-06-08 32/50 timing diagrams flash read/id read operation sram read cycle (see note 1) v ih or v il data invalid address ce2s s 1 ce oe t rc t acc t co1 t co2 t od t oh t od t oe d out valid data out t oee t coe t coe t odo hi-z hi-z ub , lb t ba t bd t be address cef oe we d out t rc t ce t acc t oee t oe t df2 t oh valid data out t df1 hi-z t cee t oeh hi-z
th50vsf3582/3583aasb 2001-06-08 33/50 sram write cycle 1 ( -controlled) (see note 4) sram write cycle 2 ( -controlled) (see note 4) we s 1 ce address t wc we t as t wr t wp ce2s t cw t cw s 1 ce valid data in d in t ds t dh d out t odw t oew hi-z ub , lb t bw see note 2 see note 5 see note 3 see note 5 address t wc s 1 ce t cw valid data in d in t ds t dh ce2s t cw we t as t wr t wp d out t coe hi-z hi-z t odw t be ub , lb t bw see note 5 see note 5
th50vsf3582/3583aasb 2001-06-08 34/50 sram write cycle 3 (ce2s-controlled) (see note 4) sram write cycle 4 ( - and -controlled) (see note 4) ub lb address t wc s 1 ce t cw valid data in d in t ds t dh ce2s t cw we t as t wr t wp d out t coe hi-z hi-z t odw t be ub , lb t bw see note 5 see note 5 address t wc s 1 ce t cw valid data in d in t ds t dh ce2s t cw we t as t wr t wp d out t coe hi-z hi-z t odw t be ub , lb t bw see note 5 see note 5
th50vsf3582/3583aasb 2001-06-08 35/50 flash command write operation this is the timing of the command write operation. the timing which described follow pages is typically same as this page?s. ? we control ? cef control address d in command address t as t cmd t wes t weh we t ah t dh t ds t celh cef t cehh command data address cef d in command address t as t cmd t ces t welh we t ceh t ah t dh t ds t wehh command data t ahw
th50vsf3582/3583aasb 2001-06-08 36/50 flash id read operation (input command sequence) address we cef d in t cmd d out bk + 00h bk + 555h 2aah 555h t rc 55h 90h t oes notes: word mode address shown bk: bank address oe bk + 01h aah manufacturer code device code hi-z read mode (input id read command sequence) id read mode address we cef d in t cmd d out 555h 2aah 555h 55h oe aah f0h id read mode (input of reset command sequence) read mode (continued) hi-z
th50vsf3582/3583aasb 2001-06-08 37/50 flash auto-program operation ( -controlled) flash auto chip erase/auto block erase operation ( -controlled) address cef we d in t cmd d out t oehp pa 555h 2aah 555h t ppw d out 7 dq t oes t vcs note: word mode address shown. pa: program address pd: program data v ccf oe pa hi-z aah 55h a0h pd we we notes: word mode address shown ba: block address for auto block erase operation cef oe we v ccf address d in aah 55h 80h aah 55h 10h/30h t cmd t oes t vcs 555h 2aah 555h 555h 2aah 555h/ba
th50vsf3582/3583aasb 2001-06-08 38/50 flash auto-program operation ( -controlled) flash auto chip erase/auto block erase operation ( -controlled) address we d in t cmd d out t oehp pa 555h 2aah 555h t ppw d out 7 dq t oes t vcs notes: word mode address shown pa: program address pd: program data v cc f oe pa hi-z aah 55h a0h pd cef cef cef oe we v ccf address d in t cmd t oes t vcs note: word mode address shown. ba: block address for auto block erase operation cef 555h 2aah 555h 555h 2aah 555h/ba 10h/30h 55h aah 80h 55h aah
th50vsf3582/3583aasb 2001-06-08 39/50 flash program/erase suspend operation flash program/erase resume operation address cef we d in d out b0h d out ra: read address bk: bank address oe hi-z by / ry t ce t oe t susp /t suse suspend mode program/erase mode hi-z ra bk pa: program address bk: bank address ba: block address ra: read address flag: hardware sequence flag address cef we d in d out oe hi-z by / ry 30h program/erase mode suspend mode hi-z ra pa/ba t oes t resp /t rese t df1 d out t df2 flag t ce t oe bk
th50vsf3582/3583aasb 2001-06-08 40/50 flash during auto-program/erase operation flash hardware reset operation flash read after address reset d out t rc t rh t acc valid data out t oh hi-z cef we by / ry t busy command input sequence during operation reset we by / ry t rp t ready t rb reset by / ry
th50vsf3582/3583aasb 2001-06-08 41/50 flash hardware sequence flag ( polling) flash hardware sequence flag (toggle bit) data address ce t cmd last command address t df1 t df2 pa/ba d in t ppw /t pcew /t pbew t oh last command data we t oehp t ce t oe dq0~dq6 invalid dq7 7 dq oe pa: program address ba: block address t busy by / ry valid valid t acc valid valid address cef oe t cmd last command address pa/ba d in last command data we t oe t oehp t oeht dq2/dq6 stop * toggle valid toggle toggle pa: program address ba: block address * dq2/dq6 stops toggling when auto operation has been completed. t busy by / ry t ppw /t pcew /t pbew t ce
th50vsf3582/3583aasb 2001-06-08 42/50 flash block protect operation address a0 a6 cef t cmd oe ba ba t oe notes: ba : block address ba + 1 : next block address * : 01h indicates that block is protected. we a1 ba + 1 t cmd t cmd t rc t pplh 60h 40h 60h 60h 01h * d in d out hi-z v ih v id t vps reset ba
th50vsf3582/3583aasb 2001-06-08 43/50 timing for switching between flash and sram modes notes: (1) we remains high during a read cycle. (2) if s 1 ce goes low (or ce2s goes high) at the same time as or after we goes low, the outputs will remain high-impedance. (3) if s 1 ce goes high (or ce2s goes low) at the same time as or before we goes high, the outputs will remain high-impedance. (4) if oe is high during a write cycle, the outputs will remain high-impedance. (5) because i/o pins may be in output state at this point, input signals of the opposite value must not be applied. (6) d out 6 stops toggling when the last command has been completed. cef ce2s t ccr t ccr s 1 ce
th50vsf3582/3583aasb 2001-06-08 44/50 sram data retention characteristics (ta = = = = -30 ~85 c) symbol parameter min typ. max unit v dh data retention supply voltage for sram 1.5 ? 3.3 v v dh = 3.3 v ta = ? 30 ~85 c ? ? 10 ta = ? 30 ~40 c ? ? 1 i ccs4 sram standby current v dh = 3.0 v ta = ? 30 ~85 c ? ? 5 a t cdr chip-deselect-to-data-retention-mode time 0 ? ? ns t r recovery time t rc (1) ? ? ns (1) read cycle time -controlled data retention mode (see note 1) ce2s-controlled data retention mode (see note 3) notes: (1) in s 1 ce -controlled data retention mode, minimum standby current mode is entered when ce2s 0.2 v or ce2s v ccs ? 0.2 v. (2) when s 1 ce is operating at the v ih level, the sram standby current is the same as i ccs3 during the transition of v ccs from 2.67 v to 2.3 v. (3) in ce2s-controlled data retention mode, minimum standby current mode is entered when ce2s 0.2 v. v ccs 2.7 v gnd s 1 ce v ih data retention mode t r (see note 2) (see note 2) t cdr v ccs v ccs ? 0.2 v s 1 ce v ccs 2.7 v gnd v il data retention mode t cdr v ccs 0.2 v v ih ce2s t r
th50vsf3582/3583aasb 2001-06-08 45/50 flowcharts of flash memory operations auto-program address = address + 1 no yes auto-program command sequence (see below) data polling or toggle bit last address? start 555h/aah 2aah/55h program address/program data 555h/a0h auto-program command sequence (address/data) note: word mode command sequence is shown. auto-program completed
th50vsf3582/3583aasb 2001-06-08 46/50 fast program address = address + 1 no yes fast program command sequence (see below) data polling or toggle bit last address? start xxxh/a0h program address/program data fast program command sequence (address/data) fast program completed fast program set command sequence (see below) program sequence (see below) 555h/aah 2aah/55h 555h/20h fast program set command sequence (address/data) xxxh/90h xxxh/f0h fast program reset command sequence (address/data)
th50vsf3582/3583aasb 2001-06-08 47/50 auto-erase auto-erase command sequence (see below) data polling or toggle bit start 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h block address/30h block address/30h block address/30h auto chip erase command sequence (address/data) auto block erase / multiple-block erase command sequence (address/data) additional block erase commands are o p eration note: word mode command sequence is shown. auto-erase completed
th50vsf3582/3583aasb 2001-06-08 48/50 dq7 ( polling) dq6 (toggle bit) data yes no yes no read byte (dq0~dq7) addr. = va read byte (dq0~dq7) addr. = va start dq7 = data? dq5 = 1? dq7 = data? no yes 1) 1) : dq7 must be rechecked even if dq5 = 1 because dq7 may change at the same time as dq5. fail pass va: byte address for programming. any of the addresses within the block being erased during a block erase operation. don ? t care during a chip erase operation. any address not within the current block during an erase suspend operation. no no no yes read byte (dq0~dq7) addr. = va read byte (dq0~dq7) addr. = va start dq6 = toggle? dq5 = 1? dq6 = toggle? yes yes 1) 1) : dq6 must be rechecked even if dq5 = 1 because dq6 may stop toggling at the same time that dq5 changes to 1. fail pass
th50vsf3582/3583aasb 2001-06-08 49/50 block protect bpa: block address and id read address (a6, a1, a0) id read address = (0, 1, 0) no no block protect command first bus write cycle (xxxh/60h) verify block protect start plscnt = 25? protect another block? wait to 100 s remove v id from reset yes no yes set up address addr. = bpa plscnt = 1 remove v id from reset plscnt = plscnt + 1 wait to 4 s reset = v id block protect command second bus write cycle (bpa/60h) block protect command third bus write cycle (xxxh/40h) yes data = 01h? reset command block protect complete reset command device failed
th50vsf3582/3583aasb 2001-06-08 50/50 package dimensions unit: mm

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